VLSI Implementation of Low Power Complex Multipliers For OFDM Transceivers

Authors : Sweenkrishna R, Ruthrapathi S, Vijayalakshmi N

Abstract

OFDM is a multi-carrier system where data bits are encoded to multiple sub-carriers, while being sent simultaneously. This results in the optimal usage of bandwidth. A set of orthogonal sub-carriers together forms an OFDM symbol. Each sub-carrier in an OFDM system is modulated in amplitude and phase by the data bits. The process of combining different sub-carriers to form a composite time-domain signal is achieved using Fast Fourier transform. In this paper an idea is proposed for implementing complex multipliers and FFT computers using bit serial approaches and distributed arithmetic concepts. Usually multiplication is done by successive additions or by design of parallel multipliers. Instead in this paper an idea of a Bit Shift Accumulation technique based on Modified BOOTH’S Algorithmis proposed to implement Complex Multipliers. By this way the speed of multiplication performed is increased and the chip area consumed is decreased which results in low power consumption. Fast Fourier transforms are taken using RADIX 4 butterfly using our Complex multiplier as and when the bit arrives thus increases the speed of OFDM transceivers.

Keywords : OFDM Transceivers; Booths algorithm; Concepts of Distributed Arithmetic; Complex Multiplier; FFT Computation; Implementation in VHDL.