Routing in Network on Chip – A Review

Authors : Sanju V , Niranjan Chiplunkar and Venkata Krishna

Abstract 

High performance systems are becoming a part and parcel of today’s life. From single core system using normal bus architecture to today we have systems with multiple cores running many applications. But the need to get more cores on a single chip is not over. The problem likes with not added more cores to the die but how do we interconnect them to give better performance. Here bus architecture fails and we need to get another design methodology in place. One of the solutions for this problem is building a chip with network on chip as the back bone. This paper tries to create a review paper on this technology.

Keywords : Network On Chip, Parallel Bus, Bus Architecture