Performance Analysis Through Simulation For Three Dimension Network On Chip Topology

Authors : Sanju V , Niranjan Chiplunkar, M Khalid, Venkata Krishna

Abstract

The growth of semiconductor devices was phenomenal in the last two decades. The device usage span from normal domestic system to cutting edge technology enabled complex digital systems. These systems were initially designed and implemented using common bus architecture which is now getting replaced by network on chip. The shrinking in device size and introduction of newer packing techniques has enabled stacking of devices into multiple levels. To understand the internal working, characteristics of the system, simulation study is one of the most popular mechanism. This paper discusses an object oriented design and implementation of a simulator for network on chip based systems for mesh, torus and SMITHA. The paper also compares the performance parameters to test the strength of the topologies.

Keywords: Network On Chip, Design, Simulator, 2D Mesh, Torus, SMITHA